Posted: January 4th, 2017

Design a phase lag compensator in series with the lead compensator designed in a. such that the steady state error resulting from a ramp input should be no greater than 3.5% of the ramp magnitude.

Design a phase lag compensator in series with the lead compensator designed in a. such that the steady state error resulting from a ramp input should be no greater than 3.5% of the ramp magnitude. Describe each stage of your design. If the overall performance specifications (listed in a. and b) are not met first time, perform another design iteration. [10 Marks]  c. Use MATLAB to plot the response of the final closed-loop compensated system to a unit magnitude ramp input, showing both system output and ramp input, and evaluate the percentage steady state error to the ramp input signal. [5 Marks]  d. Use MATLAB to evaluate the performance of your final design in the time and frequency domain. Present these in tabular form – see Table 1, and provide a written conclusion for your design.